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Catapult C Synthesis

Full-Chip C++ Synthesis

Catapult C Synthesis is a High Level Synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements.

 

Fastest Time to Verified RTL

Catapult C Synthesis reduces design time and verification effort. When writing pure C++, designers focus on the functional intent of their application. Timing and architectural information is abstracted away from the source description. With fewer details in the model, testbench development is also simplified.

Implementation of specific details are automatically added during the synthesis process, eliminating error-prone manual interventions and resulting in RTL designs correct by construction. Debug of the resulting RTL is in turn eliminated, further reducing the overall verification effort.

The Catapult C automated verification environment allows any RTL implementation of a C++ model to be verified using the original C++ testbench. This eliminates the need to write pin-level interfacing and bit-timed RTL environments to verify the RTL blocks created by Catapult before moving to system integration. Check out our Automated Verification data sheet to see how C++ accelerates your design and verification efforts.

Unifying Control-Logic and Algorithmic Synthesis

Catapult C Synthesis is the first and only tool to synthesize full hierarchical systems comprised of both control blocks and algorithmic units from pure C++.

Its unique decoupling control channel (DCC) technology combined with a patent-pending verification flow form the key technological components of a unified flow for modeling, synthesizing, and verifying the complex mix of blocks commonly found in sophisticated applications. This lets users work within a standard and homogeneous environment for the creation of complete systems from a single source representation.

Bit-Accurate Data Types

Mentor Graphics provides the AC Data Types C++ class library. This stand-alone library facilitates the use of arbitrary length bit-accurate integer and fixed point types with improved semantic consistency and faster execution times while easily coexisting with SystemC data types for verification where needed.

Even if you are just modeling bit-accurate algorithms with no intent to synthesize them, and use nothing more than a C++ compiler, a free download of the AC Data Types will provide a high speed simulation solution with fast compile times for your bit-accurate algorithms.

Synthesizing Pure ANSI C++

By using pure ANSI C++ as the design language, users can leverage many established design entry, validation and verification tools without being locked into a proprietary language or methodology.

Widely used, simple to write and, most importantly, easy to learn, C++ is the language of choice to express and synthesize complex system functionality.

Pure C++ allows for the most abstract source description. Low-level hardware details are not modeled, letting designers explore and find the optimal architecture for given performance/area/power requirements. Coupled with C++ object-oriented programming, the reuse potential of the designs is maximized and taken to levels unknown with RTL and pin-level SystemC methodologies.

As a result, designers can generate high-quality RTL with Catapult and pure C++, 10-100x faster than other methods.

 

Features and Benefits

New in Catapult C Synthesis

• Support for control-logic synthesis from pure C++
• Decoupling Control Channel (DCC) technology allows easy interfacing between algorithmic blocks and control-logic blocks
• Accuracy for control units where you need it
• Abstraction for algorithmic blocks meaning faster verification, better results
• New patent-pending SCReplay for visibility and debug during verification
• Fully automated multi-level clock-gating providing near perfect clock gating
• Dynamic power management interfaces
• Reduces power consumption by an average 40%
• ANSI C++ language synthesis with SystemC verification
• Dramatically reduces verification time through through automatic SystemC transaction level model (TLM) and testbench generation, allowing RTL tests using an untimed C++ testbench
• Create optimal hardware designs 10-100x faster than hand-coded methodologies for both control-logic and algorithmic blocks
• Significantly reduce dynamic power consumption, driven by advanced optimizations such as multi-level clock gating
• Incremental refinement methodology enables maximum user control over implementation and latency/area/throughput results
• Automatically synthesize interfaces to external hardware
• Production-proven: Over 200 ASIC tapeouts and hundreds of FPGA designs completed